An asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer protocols. This digital logic design is contrasted with a synchronous circuit which operates according to clock timing signals.
Petri nets are an attractive and powerful model for reasoning about asynchronous circuits. However Petri nets have been criticized for their lack of physical realism (see Petri net). Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model and process calculi.
The term asynchronous logic is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model - which uses 'conventional' data processing elements with completion indicated by a locally generated delay model - to delay-insensitive design - where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger than bundled data implementations, but which are insensitive to layout and parametric variations and are thus "correct by design".
Asynchronous logic is the logic required for the design of asynchronous digital systems. These function without a clock signal and so individual logic elements cannot be relied upon to have a discrete true/false state at any given time. Boolean logic is inadequate for this and so extensions are required. Karl Fant developed a theoretical treatment of this in his work Logically determined design in 2005 which used four-valued logic with null and intermediate being the additional values. Vadim Vasyukevich developed a different approach based upon a new logical operation which he called venjunction. This takes into account not only the current value of an element, but also its history.
Different classes of asynchronous circuitry offer different advantages. Below is a list of the advantages offered by Quasi Delay Insensitive (QDI) circuits, generally agreed to be the most "pure" form of asynchronous logic that retains computational universality. Less pure forms of asynchronous circuitry offer better performance at the cost of compromising one or more of these advantages:
- Robust handling of metastability of arbiters.
- Early completion of a circuit when it is known that the inputs which have not yet arrived are irrelevant.
- 70% lower power consumption compared to synchronous design
- Possibly lower power consumption because no transistor ever transitions unless it is performing useful computation (clock gating in synchronous designs is an imperfect approximation of this ideal). Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, which can result in increased power consumption if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of High-k dielectrics).
- Freedom from the ever-worsening difficulties of distributing a high-fan-out, timing-sensitive clock signal.
- Better modularity and composability.
- Far fewer assumptions about the manufacturing process are required (most assumptions are timing assumptions).
- Circuit speed adapts to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.
- Immunity to transistor-to-transistor variability in the manufacturing process, which is one of the most serious problems facing the semiconductor industry as dies shrink.
- Less severe electromagnetic interference (EMI). Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.
- In asynchronous circuits, local signaling eliminates the need for global synchronization which exploits some potential advantages in comparison with synchronous ones. They have shown potential specifications in low power consumption, design reuse, improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations.
- Less stress on the power distribution network. Synchronous circuits tend to draw a large amount of current right at the clock edge and shortly thereafter. The number of nodes switching (and thence, amount of current drawn) drops off rapidly after the clock edge, reaching zero just before the next clock edge. In an asynchronous circuit, the switching times of the nodes are not correlated in this manner, so the current draw tends to be more uniform and less bursty.
- Hardware effort may be up to double the number of circuit elements (transistors), depending on level.
- Serial designs benefit more than massively parallel ones.
- Requires people experienced in synchronous design to learn a new style.
- Synchronous designs are inherently easier to debug than asynchronous designs.
- Performance analysis of asynchronous circuits may be challenging.
Asynchronous CPUs are one of several ideas for radically changing CPU design.
Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline. Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic:
- components can run at different speeds on an asynchronous CPU; all major components of a clocked CPU must remain synchronized with the central clock;
- a traditional CPU cannot "go faster" than the expected worst-case performance of the slowest stage/instruction/component. When an asynchronous CPU completes an operation more quickly than anticipated, the next stage can immediately begin processing the results, rather than waiting for synchronization with a central clock. An operation might finish faster than normal because of attributes of the data being processed (e.g., multiplication can be very fast when multiplying by 0 or 1, even when running code produced by a naive compiler), or because of the presence of a higher voltage or bus speed setting, or a lower ambient temperature, than 'normal' or expected.
Asynchronous logic proponents believe these capabilities would have these benefits:
- lower power dissipation for a given performance level, and
- highest possible execution speeds.
The biggest disadvantage of the clockless CPU is that most CPU design tools assume a clocked CPU (i.e., a synchronous circuit). Many tools "enforce synchronous design practices". Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids metastable problems. The group that designed the AMULET, for example, developed a tool called LARD to cope with the complex design of AMULET3.
Despite the difficulty of doing so, numerous asynchronous CPUs have been built, including:
- the ORDVAC and the (identical) ILLIAC I (1951)
- the WEIZAC (1955)
- the ILLIAC II (1962)
- The Victoria University of Manchester built Atlas
- The Honeywell CPUs 6180 (1972) and Series 60 Level 68 (1981) upon which Multics ran asynchronously
- The Caltech Asynchronous Microprocessor, the world-first asynchronous microprocessor (1988);
- the ARM-implementing AMULET (1993 and 2000);
- the asynchronous implementation of MIPS R3000, dubbed MiniMIPS (1998);
- several versions of the XAP processor experimented with different asynchronous design styles: a bundled data XAP, a 1-of-4 XAP, and a 1-of-2 (dual-rail) XAP (2003?);
- an ARM-compatible processor (2003?) designed by Z. C. Yu, S. B. Furber, and L. A. Plana; "designed specifically to explore the benefits of asynchronous design for security sensitive applications";
- the "Network-based Asynchronous Architecture" processor (2005) that executes a subset of the MIPS architecture instruction set;
- the HT80C51 processor (2007???) from Handshake Solutions
- the SEAforth multi-core processor (2008) from Charles H. Moore.
- the GA144 multi-core processor (2010) from Charles H. Moore.
DEC PDP-16 Register Transfer Modules (ca. 1973) allowed the experimenter to construct asynchronous, 16-bit processing elements. Delays for each module were fixed and based on the module's worst-case timing.
The Caltech Asynchronous Microprocessor (1988) was the first asynchronous microprocessor (1988). Caltech designed and manufactured the world's first fully Quasi Delay Insensitive processor. During demonstrations, the researchers amazed viewers by loading a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate—again, with no additional configuration.
In 2004, Epson manufactured the world's first bendable microprocessor called ACT11, an 8-bit asynchronous chip. Synchronous flexible processors are slower, since bending the material on which a chip is fabricated causes wild and unpredictable variations in the delays of various transistors, for which worst case scenarios must be assumed everywhere and everything must be clocked at worst case speed. The processor is intended for use in smart cards, whose chips are currently limited in size to those small enough that they can remain perfectly rigid.
- ^ Karl M. Fant (2005), Logically determined design: clockless system design with NULL convention logic, John Wiley and Sons, ISBN 9780471684787, http://books.google.co.uk/books?id=UTHFcdvvHQcC
- ^ V.O.Vasyukevich (April, 2007), "Decoding asynchronous sequences", Automatic Control and Computer Sciences (Allerton Press) 41 (2): 93–99, doi:10.3103/S0146411607020058, ISSN 1558-108X, http://www.springerlink.com/content/e61016374u41p176/
- ^ "Epson Develops the World's First Flexible 8-Bit Asynchronous Microprocessor" 2005
- ^ "Keep It Strictly Synchronous: KISS those asynchronous-logic problems good-bye". Personal Engineering and Instrumentation News, November 1997, pages 53-55. http://www.fpga-site.com/kiss.html
- ^ "ASIC to FPGA migration"
- ^ LARD
- ^ a b c "In the 1950and 1960s, asynchronous design was used in many early mainframe computers, including the ILLIAC I and ILLIAC II ... ." Brief History of asynchronous circuit design
- ^ "The Illiac is a binary parallel asynchronous computer in which negative numbers are represented as two's complements." -- final summary of "Illiac Design Techniques" 1955.
- ^ "Entirely asynchronous, its hundred-odd boards would send out requests, earmark the results for somebody else, swipe somebody else's signals or data, and backstab each other in all sorts of amusing ways which occasionally failed (the "op not complete" timer would go off and cause a fault). ... [There] was no hint of an organized synchronization strategy: various "it's ready now", "ok, go", "take a cycle" pulses merely surged through the vast backpanel ANDed with appropriate state and goosed the next guy down. Not without its charms, this seemingly ad-hoc technology facilitated a substantial degree of overlap ... as well as the [segmentation and paging] of the Multics address mechanism to the extant 6000 architecture in an ingenious, modular, and surprising way ... . Modification and debugging of the processor, though, were no fun." "Multics Glossary: ... 6180"
- ^ "10/81 ... DPS 8/70M CPUs" Multics Chronology
- ^ "The Series 60, Level 68 was just a repackaging of the 6180." Multics Hardware features: Series 60, Level 68
- ^ a b c "A Network-based Asynchronous Architecture for Cryptographic Devices" by Ljiljana Spadavecchia 2005 in section "4.10.2 Side-channel analysis of dual-rail asynchronous architectures" and section "188.8.131.52 Instruction set"
- ^ "Handshake Solutions HT80C51" "The Handshake Solutions HT80C51 is a Low power, asynchronous 80C51 implementation using handshake technology, compatible with the standard 8051 instruction set."
- ^ SEAforth Overview "... asynchronous circuit design throughout the chip. There is no central clock with billions of dumb nodes dissipating useless power. ... the processor cores are internally asynchronous themselves."
- ^ "GreenArrayChips" "Ultra-low-powered multi-computer chips with integrated peripherals."
- ^ "Seiko Epson tips flexible processor via TFT technology" by Mark LaPedus 2005
- ^ "A flexible 8b asynchronous microprocessor based on low-temperature poly-silicon TFT technology" by Karaki et. al. 2005. Abstract: "A flexible 8b asynchronous microprocessor ACTII ... The power level is 30% of the synchronous counterpart."
- ^ "Introduction of TFT R&D Activities in Seiko Epson Corporation" by Tatsuya Shimoda (2005?) has picture of "A flexible 8-bit asynchronous microprocessor, ACT11"
- ^ "Epson Develops the World's First Flexible 8-Bit Asynchronous Microprocessor"
- ^ "Seiko Epson details flexible microprocessor: A4 sheets of e-paper in the pipeline by Paul Kallender 2005
- TiDE from Handshakesolutions in The Netherlands, Commercial asynchronous circuits design tool. Commercial asynchronous ARM(ARM996HS) and 8051(HT80C51) are available.
- An introduction to asynchronous circuit design by Davis and Nowick
- Asynchronous logic elements. Venjunction and sequention by V. O. Vasyukevich
- Null convention logic, a design style pioneered by Theseus Logic, who have fabricated over 20 ASICs based on their NCL08 and NCL8501 microcontroller cores [dead link]
- The Status of Asynchronous Design in Industry Information Society Technologies (IST) Programme, IST-1999-29119, D. A. Edwards W. B. Toms, June 2004, via www.scism.lsbu.ac.uk
- The Red Star is a version of the MIPS R3000 implemented in asynchronous logic
- The Amulet microprocessors were asynchronous ARMs, built in the 1990s at University of Manchester, England
- The N-Protocol developed by Navarre AsyncArt, the first commercial asynchronous design methodology for conventional FPGAs.
- PGPSALM an asynchronous implementation of the 6502 microprocessor
- Caltech Async Group home page
- Tiempo: Fench company providing asynchronous IP and design tools
- Epson ACT11 Flexible CPU Press Release
- Amirkabir University of Technology (Iran) asynchronous publications, FPGA, SystemC
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