Boundary scan

Boundary scan is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit.

The "Joint Test Action Group" (JTAG) developed a specification for boundary scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1994, a supplement that contains a description of the Boundary Scan Description Language (BSDL) was added which describes the boundary-scan logic content of IEEE Std 1149.1 compliant devices. Since then, this standard has been adopted by electronic device companies all over the world. Boundary scan is nowadays mostly synonymous with JTAG.

The boundary scan architecture provides a means to test interconnects and clusters of logic, memories etc. without using physical test probes. It adds one or more so called 'test cells' connected to each pin of the device that can selectively override the functionality of that pin. These cells can be programmed via the JTAG scan chain to drive a signal onto a pin and across an individual trace on the board. The cell at the destination of the board trace can then be programmed to read the value at the pin, verifying the board trace properly connects the two pins. If the trace is shorted to another signal or if the trace has been cut, the correct signal value will not show up at the destination pin, and the board will be known to have a fault.

When performing boundary scan inside integrated circuits, cells are added between logical design blocks in order to be able to control them in the same manner as if they were physically independent circuits.

For normal operation, the added boundary scan latch cells are set so that they have no effect on the circuit, and are therefore effectively invisible. However, when the circuit is set into a test mode, the latches enable a data stream to be passed from one latch to the next. Once the complete data word has been passed into the circuit under test, it can be latched into place.

As the cells can be used to force data into the board, they can set up test conditions. The relevant states can then be fed back into the test system by clocking the data word back so that it can be analysed.

By adopting this technique, it is possible for a test system to gain test access to a board. As most of today’s boards are very densely populated with components and tracks, it is very difficult for test systems to access the relevant areas of the board to enable them to test the board. Boundary scan makes this possible.

ee also

*Bed of nails tester‎
*Boundary Scan Integration into ATE-Systems

External links

* [http://www.goepel.com/en/menu-oben/jtagboundary-scan.html Pioneers of Boundary Scan IEEE 1149.1 Std.]
* [http://www.xjtag.com/jtag-technical-guide.php Brief technical guide to Boundary Scan] - An overview of the JTAG architecture.
* [http://www.corelis.com/products/Boundary-Scan_Tutorial.htm Boundary-Scan Tutorial and Applications]
* [http://www.goepelusa.com/technology.html JTAG/Boundary Scan background information and related IEEE standards]
* [http://www.boundary-scan.co.uk Boundary scan portal]
* [http://www.asset-intertech.com/pdfs/boundaryscan_tutorial.pdf Useful Boundary scan tutorial]
* [http://www.xjtag.com/docs/XJTAG_DFT_Guidelines.pdf Design for Testability (DFT) Guidelines]
* [http://www.radio-electronics.com/info/t_and_m/boundaryscan/jtag-ieee-1149-basics-tutorial.php Boundary scan tutorial with links to other boundary scan pages]
* [http://www.goepel.com/en/menu-oben/jtagboundary-scan/boundary-scan-coach.html Free interactive teaching software]
* [http://www.jtag.com/en/Support/FAQ FAQ about Boundary Scan]


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