4FDC Floppy Disk Controller
The Cromemco 4FDC
Floppy Disk Controlleris designed to interface both 5- and 8-inch floppy diskdrives to the S-100 computer bus used in Cromemcoand other IEEE 696computers. It also contains an RS232serial I/O channel with software-selectable baudrates from 110 to 76,800. In addition, it has a 1K resident 2708 ROM containing Cromemco's RDOS, the Resident Disk Operating System.
The 4FDC was designed to drive Persci 277 8-inch single-density floppy drives. These drives were interesting in two respects
* They used a fast
voice coilactuator and not a stepper motorto position the drive read write head
* The data separator electronics were on the drive itself
Due to the second fact, an unmodified 4FDC can not be used with 8-inch drives that don't have single-density data separators on the drive electronics. Later Cromemco disk controllers such as the 16FDC and 64FDC contained both single and double density data separators and the 64FDC also supplied write pre-compensation.
An aftermarket add-on board, the FDCX4 Double Density Upgrade Board for the 4FDC, was designed and marketed by JVB Electronics. The FDCX4 was a daughter board assembly that replaced the WD1771 single density disk controller chip on the 4FDC with a FD1791 (early production) or Fujitsu MB8876A (later production) double-density controller chip. The FDCX4, in addition to using an analog phase-locked-loop data separator in all modes, also used write-precompensation. These features allowed the FDCX4 equipped 4FDC to reliably use the Persci 277 drives, as well as other drives, in double-density mode.
Four switches on the 4FDC interface card are usedto set the operation of the card. Switch 1 is the RDOSDISABLE switch. When this switch is ON the lK ROMcontaining RDOS cannot be accessed by the computer.When this switch is OFF the RDOS program resides inthe computer memory space from address COOO to C3FF.
Switch 2 is the RDOS DISABLE AFTER BOOT switch. Ifthis switch is ON the lK ROM containing RDOS willautomatically be disabled after CDOS is bootstrappedin from a disk thus clearing memory space fromCOOO to C3FF for system use. (In this mode the ROMis actually disabled by an output to port 40H whichis done automatically by CDOS). If switch 2 is OFF,RDOS remains in memory space even after CDOS is loaded.
RDOS contains two programs; 1) the CDOS bootstrapprogram and 2) the console monitor program. Switch 3 isthe BOOT ENABLE switch. When this switch is ON the bootstrapprogram will execute (thus loading CDOS) withoutfirst entering the monitor program. If this switch isoff, RDOS begins in the console monitor mode permittingthe bootstrap operation or other operations to be performedunder console control.
Switch 4 is the INITIALIZATION INHIBIT switch.When this switch is ON, diskettes cannot be initializedunder software control thus preventing a "runaway," programfrom unintentionally altering the diskette initialization.This switch must be OFF when initializing diskettes.
Western DigitalFD1771-1 Interfaces
All signals from the drives are
TTL.buffered. and have150 Ω pullups. Maxi and mini signals are wired and atthe pullup side of the buffers. Signals which. do not applyto the mini (i.e. ,.READY and SEP CLOCK), are disabled andpulled high when the mini is selected. Signals to the drives from the 1771 are TTL bufferedwith separate buffers for mini and. maxi connectors. TheSTEP output is stretched by IC37 to about 16 microsecondsbefore going to the .drives.. The HLD (head load) output doesnot go directly to the drives but rather enables the driveselect lines through IC10 Pin1. Thus, the actual drive selectsignal to the drive is the coincidence of a latched driveselection (done at port 34H) and HLD from the 1771. Headloading time is determined by counters IC36. and 27. timeout is controlled by the count loaded into lC3'S by IC53.Signals DRQ, HLD, and INTRQ (or EOJ) are available atinput port 34H (rC9). Various control signals are assignedto output port 34H and are latched by rcs 24 and 41.
Board Priority Chain
The 4FDC includes a ripple priority circuit which willdefeat the interrupt acknowledge cycle of Priority IN/ isheld low. If the 4FDC is allowed to perform the interruptacknowledge, it will pull down its Priority Out/ line tosignal others in the chain not to respond. This chain iscompatible with the Cromemco TU-ART.
* [http://vt100.net/mirror/harte/Cromemco/Cromemco%204FDC%20Manual%201977.pdf Controller Manual in PDF Format]
* [http://maben.homeip.net:8217/static/S100/cromemco/cards/Cromemco%204FDC%20Disk%20Controller%201977.pdf More details of the switch setting used to configure this card as well as the theory of operation]
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