Self-aligned gate

A self-aligned gate is a design arrangement where a highly doped gate in a MOSFET is used as a mask for the doping of the source and drain around it. This technique ensures that the gate will always overlap the edges of the source and drain. The use of self-aligned gates is one of the many innovations that has enabled computing power to increase steadily over the last 40 years.

Introduction

The self-aligned gate is used to improve the accuracy of the entire fabrication process. cite book
coauthors = Yanda, Heynes, and Miller
title = Demystifying Chipmaking
date = 2005
pages = 148-149
isbn = 0750677600
] As devices became smaller and smaller during the seventies there was a need for a more precise and reliable way to fabricate MOSFETS. The gate regions would sometimes fail to overlap the source and drain. This results in a non-working MOSFET. The solution was to create a new process that would eliminate the possibility of the gate not overlapping the source and drain. This solution was called self-aligned gate technology.

Innovations that made Self-Aligned Gate Technology possible

Certain innovations were required in order to make self-aligned gates. cite book
last = Orton
first = John Wilfred
title = The Story of Semiconductors
date = 2004
pages = 114
isbn = 0198530838
]

1. A new process that would create the gates.

2. A switch from amorphous silicon to polycrystalline silicon. This is because amorphous silicon broke down during the oxide steps.

3. A method for etching polycrystalline silicon. (Photolithography)

4. A method to reduce the impurities present in silicon.

Without these innovations, self-aligned gates would not have been possible.

History

The self-aligned gate design was patented in 1969 by the team of Kerwin, Klein, and Sarace. Citation | first = R. E. | last = Kerwin | first2 = D. L. | last2 = Klein | first3 = J. C. | last3 = Sarace | contribution = Method for Making MIS Structure | title = U.S. Patent 3,475,234 | year = 1969 ] Actually the self-aligned gate MOSFET was invented by Robert W. Bower U.S. 3,472,712, issued October 14, 1969, Filed October 27, 1966. The Bell Labs Kerwin et al patent 3,475,234 was not filed until March 27, 1967 several months after the R. W. Bower and H. D. Dill Published and presented the first publication of this work at the International Electron Device Meeting, Washington, D.C., 1966. However, in a legal action involving Bower and Dill, the Third Circuit Court of Appeals determined that Kerwin Klein and Sarace were the true inventors of the self-algned silicon gate transistor. On that basis they were awarded the basic patent US 3,475,234. The US patent system awards the basic patent to the party that first makes the invention not the party that first files a patent application.

This work entitled INSULATED GATE FIELD EFFECT TRANSISTORS FABRICATED USING THE GATE AS SOURCE-DRAIN MASK, Paper 16.6 International Electron Device Meeting, Washington, D.C., 1966 described the self aligned-gate MOSFET made with both aluminum and polysilicon gate using both ion implantation and diffusion to form the source and drain using the gate electrode as the mask to define the source and drain regions. The Bell Labs team attended this meeting of the IEDM in 1966 and discussed this work with Bower after his presentation in 1966. Bower believed he first made the self-aligned gate using aluminum as the gate and before presentation in 1966 made the device using polysilicon as the gate. However, he was not able to prove it to the courts.

Description of Process

The importance of self-aligned gates comes in the process used to make them. The process of using the gate oxide as a mask for the source and drain diffusion both simplifies the process and greatly improves the yield.

Process Steps cite book | last = Streetman | first = Ben | coauthors = Banerjee | title = Solid State Electronic Devices | publisher = PHI | date = 2006 | pages = 269-27, 313
isbn = 81-203-3020-X
]

1. Start with a bare silicon wafer.

2. Using a dry thermal oxidation process, a thin layer (5-200nm) of gate oxide is grown on the silicon wafer, usually SiO2.

3. Using a Chemical vapor deposition (CVD) process, a layer of polysilicon is grown on top of the gate oxide.

4. A layer of photoresist is applied on top of the polysilicon.

5. A mask is placed on top of the photoresist and exposed to UV Light, this breaks down the photoresist where the mask didn't protect it.

6. Photoresist is exposed with a specialized developer solution. This should remove the photoresist that was broken down by the UV light.

7. The polysilicon and gate oxide that is not covered by photoresist is etched away with a buffered ion etch process. This is usually an acid solution containing Hydrofluoric acid.

8. The rest of the photoresist is stripped from the silicon wafer. There is now a wafer with a small rectangle of polysilicon and gate oxide.

9. The area outside the gate (the source and drain) is doped using a process called ion-implantation. This effectively uses the gate region as a mask for the implantation process.

10. The wafer is annealed in a high temperature furnace (>convert|800|°C|°F|sigfig=2). This allows the source and drain to diffuse underneath the gate.

ee also

MOSFET

Semiconductor device fabrication

Microfabrication

References


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