Floating Gate MOSFET

The Floating Gate MOSFET (FGMOS) is a field effect transistor, whose structure is similar to a conventional MOSFET. The gate of the FGMOS is electrically isolated, creating a floating node in DC, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG. Since the FG is completely surrounded by highly resisitve material, the charge contained in it remains unchanged for long periods of time. Usually Fowler-Nordheim Tunneling and Hot-Carrier Injection mechanisms are used in order to modify the amount of charge stored in the FG.

Some applications of the FGMOS are digital storage element in EPROM, EEPROM and FLASH memories, neuronal computational element in neural networks, analog storage element, e-Pots and single-transistor DACs.

History

The first report of a Floating Gate MOSFET was made by Kahng and Sze, [D. Kahng and S.M. Sze, "A floating-gate and its application to memory devices," The Bell System Technical Journal, vol. 46, no. 4, 1967, pp. 1288-1295] and dates back to 1967. The first application of the FGMOS was to store digital data in EEPROM, EPROM and FLASH memories. However, the current interest in FGMOS circuits started from developing large-scale computations in neuromorphic systems, which are inherently analog.

In 1989 Intel employed the FGMOS as an analog nonvolatile memory element in his ETANN chip, [M. Holler, S. Tam, H. Castro, and R. Benson, "An electrically trainable artificial neural network with 10240 'floating gate' synapses," Proceeding of the International Joint Conference on Neural Networks, Washington, D.C., vol. II, 1989, pp. 191-196] demonstrating the potential of using FGMOS devices for applications other than digital memory.

Three research accomplishments laid the groundwork for much of the current FGMOS circuit development:
# Thomsen and Brooke's demonstration and use of electron tunneling in a standard CMOS double-poly process [A. Thomsen and M.A. Brooke, "A floating gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process," IEEE Electron Device Letters, vol. 12, 1991, pp. 111-113] allowed many researchers to investigate FGMOS circuits concepts without requiring access to specialized fabrication processes.
# The "ν"MOS, or neuron-MOS, circuit approach by Shibata and Ohmi [T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations," IEEE Transactions on Electron Devices, vol. 39, no. 6, 1992, pp. 1444-1455] provided the initial inspiration and framework to use capacitors for linear computations. These researchers concentrated on the FG circuit properties instead of the device properties, and used either UV light to equalize charge, or simulated FG elements by opening and closing MOSFET switches.
# Carver Mead's adaptive retina [C.A. Mead and M. Ismail, editors, Analog VLSI Implementation of Neural Systems, Kluwer Academic Publishers, Norwell, MA, 1989] gave the first example of using continuously-operating FG programming/erasing techniques, in this case UV light, as the backbone of an adaptive circuit technology.

Structure

An FGMOS can be fabricated by electrically isolating the gate of a standard MOS transistor, so that there are no resistive connections to its gate. A number of secondary gates or inputs are then deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG, since the FG is completely surrounded by highly resistive material. So, in terms of its DC operating point, the FG is a floating node.

Theory of Operation

Large Signal DC

Small Signal

Charge Accumulation

Applications

See also

* MOSFET

References and Notes


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