The electric circuit extraction or simply circuit extraction, also netlist extraction, is the translation of an integrated circuit layout back into the electrical circuit (netlist) it is intended to represent. This extracted circuit is needed for various purposes including circuit simulation, static timing analysis, signal integrity, power analysis and optimization, and logic to layout comparison. Each of these functions requires a slightly different representation of the circuit, resulting in the need for multiple layout extractions. In addition, there may be a postprocessing step of converting the device-level circuit into a purely digital circuit, but this is not considered part of the extraction process.
The detailed functionality of an extraction process will depend on its system environment. The simplest form of extracted circuit may be in the form of a netlist, which is formatted for a particular simulator or analysis program. A more complex extraction may involve writing the extracted circuit back into the original database containing the physical layout and the logic diagram. In this case, by associating the extracted circuit with the layout and the logic network, the user can cross-reference any point in the circuit to its equivalent points in the logic and layout (cross-probing). For simulation or analysis, various formats of netlist can then be generated using programs that read the database and generate the appropriate text information.
In extraction, it is often helpful to make an (informal) distinction between designed devices, which are devices that are deliberately created by the designer, and parasitic devices, which were not explicitly intended by the designer but are inherent in the layout of the circuit.
Primarily there are three different parts to the extraction process. These are designed device extraction, interconnect extraction, and parasitic device extraction. These parts are inter-related since various device extractions can change the connectivity of the circuit, e.g., resistors (whether designed or parasitic) convert single nets into multiple electrical nodes. Usually one level of interconnect extraction is used with designed device extraction to provide a circuit for simulation or gate-level reduction, and a second level of interconnect extraction is used with parasitic device extraction to provide a circuit for timing analysis.
Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin and Scheffer, ( ISBN 0-8493-3096-3 ) A survey of the field of electronic design automation. This summary was derived, with permission, from Volume II, Chapter 22, Layout Extraction, by William Kao, Chi-Yuan Lo, Mark Basel, Raminderpal Singh, Peter Spink, and Lou Scheffer.
Wikimedia Foundation. 2010.
Look at other dictionaries:
Application-specific integrated circuit — An application specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general purpose use. For example, a chip designed solely to run a cell phone is an ASIC.In contrast, the… … Wikipedia
Intact dilation and extraction — (IDX, intact D X, et al.) Background Abortion type Surgical First use 1983 Gestation >16 weeks Usage United States 0.17% ( … Wikipedia
Copper extraction techniques — This article is about historical production methods. For modern methods, see Flash smelting. The Chino open pit copper mine in New Mexico … Wikipedia
Closed-circuit television — CCTV redirects here. For other uses, see CCTV (disambiguation). For the Chinese television station, see China Central Television. Surveillance cameras on a corner. Closed circuit television (CCTV) is the use of video cameras to transmit a signal… … Wikipedia
Cobalt extraction techniques — Cobalt ore Several methods exist for the separation of cobalt from copper and nickel. They depend on the concentration of cobalt and the exact composition of the used ore. Contents … Wikipedia
Applied Wave Research — Applied Wave Research, Inc. (AWR) is an electronic design automation (EDA) software company, founded by Dr. Joseph E. Pekarek. AWR is headquartered in Los Angeles, Californiawith research and development centers in: San Jose, California; Boulder … Wikipedia
List of books in computational geometry — This is a list of books in computational geometry. There are two major, largely nonoverlapping categories: *Combinatorial computational geometry, which deals with collections of discrete objects or defined in discrete terms: points, lines,… … Wikipedia
Largest empty rectangle — In computational geometry, the largest empty rectangle problem, maximal empty rectangle problem or maximum empty rectangle problem, is the problem of finding a rectangle of maximal size to be placed among obstacles in the plane. There… … Wikipedia
Conception de circuits intégrés — La conception (ou le design) de circuits intégrés (ou puces électroniques) consiste à réaliser les nombreuses étapes de développement (flot de conception ou design flow) nécessaires pour concevoir correctement et sans erreurs une puce… … Wikipédia en Français
Conception De Circuits Intégrés — La conception (ou le design) de circuits intégrés (ou puces électroniques) consiste à réaliser les nombreuses étapes de développement (flot de conception ou design flow) nécessaires pour concevoir correctement et sans erreurs une puce… … Wikipédia en Français